From 4e0ec592553fd94e14a239eeb05ba9ccb668b814 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 6 Jun 2019 10:07:17 +0200 Subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/braswell/include/soc/bootblock.h | 22 ++++++++++++++++++++++ src/soc/intel/braswell/include/soc/romstage.h | 4 +--- 2 files changed, 23 insertions(+), 3 deletions(-) create mode 100644 src/soc/intel/braswell/include/soc/bootblock.h (limited to 'src/soc/intel/braswell/include') diff --git a/src/soc/intel/braswell/include/soc/bootblock.h b/src/soc/intel/braswell/include/soc/bootblock.h new file mode 100644 index 0000000000..e6e25ccbb1 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/bootblock.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BOOTBLOCK_H_ +#define _SOC_BOOTBLOCK_H_ + +void set_max_freq(void); + +#endif /* _SOC_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 4ecbd2c1f9..9fad9bc5a0 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -23,12 +23,10 @@ #include void gfx_init(void); -void tco_disable(void); void punit_init(void); void set_max_freq(void); -/* romstage_common.c functions */ -void program_base_addresses(void); +/* romstage.c functions */ int chipset_prev_sleep_state(struct chipset_power_state *ps); /* Values for FSP's PcdMemoryTypeEnable */ -- cgit v1.2.3