From 2c63017ca356bd245b3b09d1001586c019f5fa05 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Tue, 2 Apr 2019 15:06:29 +0200 Subject: soc/intel/braswell: Correct serial IRQ support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Serial IRQ was configured in quiet mode, but not enabled. Enable serial IRQ and use 'enum seriirq_mode' as a devicetree option. Function sc_enable_serial_irqs() is added to enabled serial IRQs. enable_serirq_quiet_mode() is renamed to sc_set_serial_irqs_mode(). This function use the 'serirq_mode' to set the mode. The call to this function is moved from finalize to init having serial IRQs enable in early stage. Serial IRQs must be enabled in continuous mode for at least one frame before switching into quiet mode. BUG=N/A TEST=Portwell PQ7-M107 Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/29398 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/soc/intel/braswell/include/soc/lpc.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/braswell/include') diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h index 7b1e3424e9..1a56f9e8c1 100644 --- a/src/soc/intel/braswell/include/soc/lpc.h +++ b/src/soc/intel/braswell/include/soc/lpc.h @@ -31,6 +31,10 @@ #define UART_CONT 0x80 #define RCBA 0xf0 +/* iLB Memory Mapped IO */ +#define ILB_OIC 0x60 +#define SIRQEN (1 << 12) + /* Memory Mapped IO in LPC bridge */ #define SCNT 0x10 #define SCNT_MODE (1 << 7) /* When cleared, SERIRQ is in quiet mode */ -- cgit v1.2.3