From 132bbe6be537b5cb8e827e01f28086d3e3ce6677 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 1 Jul 2017 13:02:47 -0500 Subject: soc/intel/braswell: Save/restore GMA OpRegion address Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to save the ACPI OpRegion table address in ASLB, and restore table address upon S3 resume. Implementation modeled on existing Baytrail code. Test: boot Windows 10 on google/edgar with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/25197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/braswell/include/soc/nvs.h | 37 +++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/braswell/include') diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 9b921c54a7..89a434bf8b 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -63,7 +63,42 @@ typedef struct global_nvs_t { u32 cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd3[196]; + u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ + + /* IGD OpRegion */ + u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ + u8 ibtt; /* 0xb8 - IGD boot type */ + u8 ipat; /* 0xb9 - IGD panel type */ + u8 itvf; /* 0xba - IGD TV format */ + u8 itvm; /* 0xbb - IGD TV minor format */ + u8 ipsc; /* 0xbc - IGD Panel Scaling */ + u8 iblc; /* 0xbd - IGD BLC configuration */ + u8 ibia; /* 0xbe - IGD BIA configuration */ + u8 issc; /* 0xbf - IGD SSC configuration */ + u8 i409; /* 0xc0 - IGD 0409 modified settings */ + u8 i509; /* 0xc1 - IGD 0509 modified settings */ + u8 i609; /* 0xc2 - IGD 0609 modified settings */ + u8 i709; /* 0xc3 - IGD 0709 modified settings */ + u8 idmm; /* 0xc4 - IGD Power Conservation */ + u8 idms; /* 0xc5 - IGD DVMT memory size */ + u8 if1e; /* 0xc6 - IGD Function 1 Enable */ + u8 hvco; /* 0xc7 - IGD HPLL VCO */ + u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ + u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ + u8 pavp; /* 0xe9 - IGD PAVP data */ + u8 rsvd12; /* 0xea - rsvd */ + u8 oscc; /* 0xeb - PCIe OSC control */ + u8 npce; /* 0xec - native pcie support */ + u8 plfl; /* 0xed - platform flavor */ + u8 brev; /* 0xee - board revision */ + u8 dpbm; /* 0xef - digital port b mode */ + u8 dpcm; /* 0xf0 - digital port c mode */ + u8 dpdm; /* 0xf1 - digital port c mode */ + u8 alfp; /* 0xf2 - active lfp */ + u8 imon; /* 0xf3 - current graphics turbo imon value */ + u8 mmio; /* 0xf4 - 64bit mmio support */ + + u8 unused[11]; /* ChromeOS specific (0x100-0xfff) */ chromeos_acpi_t chromeos; -- cgit v1.2.3