From 4e6b7907de07c9c7d4b01a6213a8e13e946398cb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 2 Oct 2018 08:44:47 +0200 Subject: src: Fix MSR_PKG_CST_CONFIG_CONTROL register name Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/soc/intel/braswell/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/braswell/cpu.c') diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 85b04ac81f..6ed12afa5f 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -36,7 +36,7 @@ /* Core level MSRs */ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), + REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), /* Disable C1E */ -- cgit v1.2.3