From aff502e87ae57fa2dc09367d00f143b6befb9530 Mon Sep 17 00:00:00 2001 From: fdurairx Date: Fri, 21 Aug 2015 15:36:53 -0700 Subject: soc/braswell: Fix DSP clock The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams Original-Reviewed-by: Aaron Durbin Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/braswell/chip.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/braswell/chip.h') diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 0f3c1d0220..6eb1451b2e 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -33,6 +33,11 @@ #define MEM_DDR3 0 #define MEM_LPDDR3 1 +enum lpe_clk_src { + LPE_CLK_SRC_XTAL, + LPE_CLK_SRC_PLL, +}; + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; @@ -41,8 +46,7 @@ struct soc_intel_braswell_config { int disable_slp_x_stretch_sus_fail; /* LPE Audio Clock configuration. */ - int lpe_codec_clk_freq; /* 19 or 25 are valid. */ - int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */ /* Native SD Card controller - override controller capabilities. */ uint32_t sdcard_cap_low; -- cgit v1.2.3