From 348a6d519c9b42f0bbe211f8e550d06aa7d5c210 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Thu, 30 Jun 2016 14:50:52 +0800 Subject: soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de. Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC. Ensure PerPortRXISet UPD offsets align with FSP. Ensure UPD values not defined in devicetree.cb are referred from *.dsc. Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35 Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf Original-Reviewed-by: Aaron Durbin Original-Tested-by: Keith Tzeng Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/21373 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/braswell/chip.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/braswell/chip.h') diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index c661bb402a..9fde4d12a6 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -168,6 +168,11 @@ struct soc_intel_braswell_config { UINT8 I2C4Frequency; UINT8 I2C5Frequency; UINT8 I2C6Frequency; + UINT8 D0Usb2Port0PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port1PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port2PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port3PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port4PerPortRXISet; /*setting for D0 stepping SOC*/ }; extern struct chip_operations soc_intel_braswell_ops; -- cgit v1.2.3