From 32471729d9ebbabe809711ec55568925c6ce2070 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Mon, 20 Apr 2015 15:20:28 -0700 Subject: Braswell: Add Braswell SOC support Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/braswell/acpi/dptf/cpu.asl | 86 ++++++++++++++++++++++---------- 1 file changed, 60 insertions(+), 26 deletions(-) (limited to 'src/soc/intel/braswell/acpi/dptf/cpu.asl') diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 58c1c7bea7..9b1930b926 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -1,13 +1,13 @@ -External (\_PR.CP00._TSS, MethodObj) -External (\_PR.CP00._TPC, MethodObj) -External (\_PR.CP00._PTC, PkgObj) -External (\_PR.CP00._TSD, PkgObj) -External (\_PR.CP00._PSS, MethodObj) - -Device (TCPU) +External (\_PR.CPU0._TSS, MethodObj) +External (\_PR.CPU0._TPC, MethodObj) +External (\_PR.CPU0._PTC, PkgObj) +External (\_PR.CPU0._TSD, PkgObj) +External (\_PR.CPU0._PSS, MethodObj) +External (\_SB.DPTF.CTOK, MethodObj) + +Device (B0DB) { - Name (_HID, EISAID ("INT3401")) - Name (_UID, 0) + Name (_ADR, 0x000B0000) /* Bus 0, Device B, Function 0 */ Method (_STA) { @@ -24,8 +24,8 @@ Device (TCPU) Method (_TSS) { - If (CondRefOf (\_PR.CP00._TSS)) { - Return (\_PR.CP00._TSS) + If (CondRefOf (\_PR.CPU0._TSS)) { + Return (\_PR.CPU0._TSS) } Else { Return (Package () { @@ -36,8 +36,8 @@ Device (TCPU) Method (_TPC) { - If (CondRefOf (\_PR.CP00._TPC)) { - Return (\_PR.CP00._TPC) + If (CondRefOf (\_PR.CPU0._TPC)) { + Return (\_PR.CPU0._TPC) } Else { Return (0) } @@ -45,8 +45,8 @@ Device (TCPU) Method (_PTC) { - If (CondRefOf (\_PR.CP00._PTC)) { - Return (\_PR.CP00._PTC) + If (CondRefOf (\_PR.CPU0._PTC)) { + Return (\_PR.CPU0._PTC) } Else { Return (Package () { @@ -58,8 +58,8 @@ Device (TCPU) Method (_TSD) { - If (CondRefOf (\_PR.CP00._TSD)) { - Return (\_PR.CP00._TSD) + If (CondRefOf (\_PR.CPU0._TSD)) { + Return (\_PR.CPU0._TSD) } Else { Return (Package () { @@ -70,8 +70,8 @@ Device (TCPU) Method (_TDL) { - If (CondRefOf (\_PR.CP00._TSS)) { - Store (SizeOf (\_PR.CP00._TSS ()), Local0) + If (CondRefOf (\_PR.CPU0._TSS)) { + Store (SizeOf (\_PR.CPU0._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -98,8 +98,8 @@ Device (TCPU) Method (_PSS) { - If (CondRefOf (\_PR.CP00._PSS)) { - Return (\_PR.CP00._PSS) + If (CondRefOf (\_PR.CPU0._PSS)) { + Return (\_PR.CPU0._PSS) } Else { Return (Package () { @@ -113,8 +113,8 @@ Device (TCPU) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CP00._PSS)) { - Store (SizeOf (\_PR.CP00._PSS ()), Local0) + } ElseIf (CondRefOf (\_PR.CPU0._PSS)) { + Store (SizeOf (\_PR.CPU0._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -127,18 +127,52 @@ Device (TCPU) { Return (\_SB.MPPC) } - #ifdef DPTF_CPU_CRITICAL Method (_CRT) { - Return (^^CTOK (DPTF_CPU_CRITICAL)) + Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL)) } #endif #ifdef DPTF_CPU_PASSIVE Method (_PSV) { - Return (^^CTOK (DPTF_CPU_PASSIVE)) + Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4)) } #endif } -- cgit v1.2.3