From 863853cd2d8e01db2045e73d96c502e4ecba8ad1 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Tue, 18 Jun 2019 12:18:55 +0200 Subject: soc/intel/braswell/smbus.c: Add support for i2c mode block write MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel Braswell supports i2c block write using SMBus controller. smbus_i2c_block_write() is added to configure SMBus controller in i2c mode before calling do_i2c_block_write(). Add smbus.c to ramstage. BUG=N/A TEST=Verify LCD display is working on Facebook FBG-1701 Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/33225 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/braswell/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/braswell/Makefile.inc') diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 1017d80c65..cc111da485 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -35,6 +35,7 @@ ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += emmc.c ramstage-y += gpio.c ramstage-y += gfx.c +ramstage-y += smbus.c ramstage-y += gpio_support.c ramstage-y += iosf.c -- cgit v1.2.3