From f677d17ab3cfd1471c0f238a0d32b0d56dd8d37f Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 1 Oct 2018 19:17:11 +0200 Subject: intel: Use CF9 reset (part 2) Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also implement board_reset() as a "full reset" (aka. cold reset) as that is what was used here for hard_reset(). Drop soc_reset_prepare() thereby, as it was only used for APL. Also, move the global-reset logic. We leave some comments to remind us that a system_reset() should be enough, where a full_reset() is called now (to retain current behaviour) and looks suspicious. Note, as no global_reset() is implemented for Denverton-NS, we halt there now instead of issuing a non-global reset. This seems safer; a non-global reset might result in a reset loop. Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/29169 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/braswell/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/intel/braswell/Kconfig') diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 2799e5b9af..2ba79926ea 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER - select HAVE_HARD_RESET select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM -- cgit v1.2.3