From f555a58abc487270d4ba42527b1b43850bd718c0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Mon, 6 Jan 2020 19:41:42 +0200
Subject: sb/intel/common: Declare common smbus_base() and enable_smbus()
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This avoids including platform-specific headers with different
filenames from common code.

Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/baytrail/romstage/raminit.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'src/soc/intel/baytrail')

diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 62f8e42134..c21a0c4acb 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
+#include <device/smbus_host.h>
 #include <mrc_cache.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
@@ -32,13 +33,18 @@
 #include <ec/google/chromeec/ec_commands.h>
 #include <security/vboot/vboot_common.h>
 
-static void enable_smbus(void)
+uintptr_t smbus_base(void)
+{
+	return SMBUS_BASE_ADDRESS;
+}
+
+int smbus_enable_iobar(uintptr_t base)
 {
 	uint32_t reg;
 	const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
 
 	/* SMBus I/O BAR */
-	reg = SMBUS_BASE_ADDRESS | 2;
+	reg = base | 2;
 	pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg);
 	/* Enable decode of I/O space. */
 	reg = pci_read_config16(smbus_dev, PCI_COMMAND);
@@ -52,6 +58,8 @@ static void enable_smbus(void)
 	/* Configure pads to be used for SMBus */
 	score_select_func(PCU_SMB_CLK_PAD, 1);
 	score_select_func(PCU_SMB_DATA_PAD, 1);
+
+	return 0;
 }
 
 static void ABI_X86 send_to_console(unsigned char b)
-- 
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