From c5bcd28554ff0a1e5dda13742feb9024a195cb8b Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Tue, 7 Jul 2020 18:16:35 +0200
Subject: soc/intel/baytrail/smm.c: Align with Braswell

This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43199
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/baytrail/smm.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/soc/intel/baytrail')

diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index af85c8209e..3f3c53fa74 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
 #include <arch/io.h>
 #include <device/mmio.h>
+#include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/smm_reloc.h>
+#include <device/device.h>
+#include <device/pci.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
 #include <soc/smm.h>
@@ -60,9 +60,9 @@ static void smm_southcluster_route_gpios(void)
 
 	/* Enable SMIs for the gpios that are set to trigger the SMI. */
 	for (i = 0; i < 16; i++) {
-		if ((route_reg & ROUTE_MASK) == ROUTE_SMI) {
+		if ((route_reg & ROUTE_MASK) == ROUTE_SMI)
 			alt_gpio_reg |= (1 << i);
-		}
+
 		route_reg >>= 2;
 	}
 	printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg);
-- 
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