From 8ef2a45bb9139a160d2562938680a73edb10e8ae Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 18 May 2019 15:51:39 -0500 Subject: soc/{baytrail/braswell/broadwell}: fix flashconsole on platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enabling flashconsole on these platforms fails to build due to spi.c not being compiled in prior to ramstage. Include in early stages (bootblock/romstage/postcar) as needed to enable flashconsole support. Early inclusion of monotonic_timer.c is needed for Broadwell as well. Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/32878 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/baytrail/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/baytrail') diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 0d4bac5140..6e6eb9cc44 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -16,6 +16,8 @@ ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c smm-y += tsc_freq.c +romstage-y += spi.c +postcar-y += spi.c ramstage-y += spi.c smm-y += spi.c ramstage-y += chip.c -- cgit v1.2.3