From 81100bf7ff62c4ee53214afb82f2fa9112d109b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 16 Aug 2019 10:37:15 +0300 Subject: soc/intel: Move fill_postcar_frame to memmap.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894 Reviewed-by: Angel Pons Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/memmap.c | 15 +++++++++++++++ src/soc/intel/baytrail/romstage/romstage.c | 13 ------------- 2 files changed, 15 insertions(+), 13 deletions(-) (limited to 'src/soc/intel/baytrail') diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 015f13c503..d9f6160dfc 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -13,7 +13,9 @@ * GNU General Public License for more details. */ +#include #include +#include #include #include @@ -37,3 +39,16 @@ void smm_region(uintptr_t *start, size_t *size) *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; *size = smm_region_size(); } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 2b92c32f3a..80915fdca0 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -240,16 +240,3 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { romstage_main(base_timestamp); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); -} -- cgit v1.2.3