From 766482d320e5ec861e72fdb933d73bdfa72c1fb4 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 9 Jan 2014 10:44:06 -0600 Subject: baytrail: don't SMI on tco timer firing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SMI on TCO timer timeout policy was copied from other chipsets. However, it's not very advantageous to have the TCO timer timeout trigger an SMI unless the firmware was the one responsible for setting up the timer. BUG=chromium:321832 BRANCH=rambi,squawks TEST=Manually enabled TCO timer. TCO fires and logged in eventlog. Change-Id: I420b14d6aa778335a925784a64160fa885cba20f Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/181985 Reviewed-on: http://review.coreboot.org/5035 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/baytrail/smm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/baytrail') diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 1fb35d7616..d4b3d58350 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -102,14 +102,14 @@ void southcluster_smm_enable_smi(void) southcluster_smm_route_gpios(); /* Enable SMI generation: - * - on TCO events * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) * No SMIs: + * - on TCO events * - on microcontroller writes (io 0x62/0x66) */ - enable_smi(TCO_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -- cgit v1.2.3