From 544878b56349a74e8cb7a0e9af899b5f7fc246fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 9 Aug 2019 11:41:15 +0300 Subject: arch/x86: Add postcar_frame_common_mtrrs() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/romstage/romstage.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'src/soc/intel/baytrail') diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index acdf2613fa..8361bb1972 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -62,6 +62,8 @@ static void prepare_and_run_postcar(struct postcar_frame *pcf) fill_postcar_frame(pcf); + postcar_frame_common_mtrrs(pcf); + run_postcar_phase(pcf); /* We do not return here. */ } @@ -256,12 +258,6 @@ static void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. -- cgit v1.2.3