From 12baf2057c6ab14f3229a440d003d6acdeb512fe Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 7 Jul 2020 17:51:17 +0200 Subject: soc/intel/baytrail/lpe.c: Align with Braswell This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: If75b4299918f5bee3cc68bc662d03f1a819aef68 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43194 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/lpe.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/baytrail') diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index e31e15e881..29633e57ee 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -44,11 +44,12 @@ static void lpe_enable_acpi_mode(struct device *dev) static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR16(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), + /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, - LPE_PCICFGCTR1_PCI_CFG_DIS | - LPE_PCICFGCTR1_ACPI_INT_EN), + LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN), + REG_SCRIPT_END }; struct global_nvs *gnvs; @@ -123,7 +124,7 @@ static void lpe_stash_firmware_info(struct device *dev) } /* Continue using old way of informing firmware address / size. */ - pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); + pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); /* C0 and later steppings use an offset in the MMIO space. */ -- cgit v1.2.3