From 19edc3a2e53eb54994a99ca8a868480badcbf227 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 9 Jan 2014 11:17:37 -0600 Subject: baytrail: clear the pmc wake status registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PMC in baytrail maintains an additional set wake status in memory-mapped registers. If these bits aren't cleared the device won't be able to go to S5 or S3 without being immediately woken up. Therefore clear these registers. BUG=chrome-os-partner:24913 BRANCH=rambi,squawks TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work correctly. Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/181984 Reviewed-on: http://review.coreboot.org/5034 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/baytrail/smm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/baytrail/smm.c') diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index e10c70b699..1fb35d7616 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -62,6 +62,7 @@ void southcluster_smm_clear_state(void) clear_tco_status(); clear_gpe_status(); clear_alt_status(); + clear_pmc_status(); } static void southcluster_smm_route_gpios(void) -- cgit v1.2.3