From 0778c86b3b94490284d0fe686500d29ca791d39d Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 10 Jun 2020 12:44:03 +0300 Subject: sb,soc/intel: Replace smm_southbridge_enable_smi() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/baytrail/smm.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/baytrail/smm.c') diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 38efe2ba39..58238db627 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -70,9 +70,8 @@ static void smm_southcluster_route_gpios(void) outl(alt_gpio_reg, alt_gpio_smi); } -void smm_southbridge_enable_smi(void) +static void smm_southbridge_enable(uint16_t pm1_events) { - uint16_t pm1_events = PWRBTN_EN | GBL_EN; printk(BIOS_DEBUG, "Enabling SMIs.\n"); if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE]) @@ -94,6 +93,11 @@ void smm_southbridge_enable_smi(void) enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } +void global_smi_enable(void) +{ + smm_southbridge_enable(PWRBTN_EN | GBL_EN); +} + void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* -- cgit v1.2.3