From 6f9947a3ec2cf481dbb233660a29f757a8707cf8 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 18 Nov 2013 11:16:20 -0600 Subject: baytrail: enable caching and prefetching in spi controller The default mode of the SPI controller has prefetching disabled. That obviously has a performance impact. Enable both caching and prefetching to make booting faster. This has a significant impact on streaming data out of SPI. BUG=chrome-os-partner:24085 BRANCH=None TEST=Built and booted rambi. Payload loading step went from ~285ms to ~54ms. Change-Id: I065cf44e1de7dcefc49aa9ea9ad0204929ab26f4 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/177220 Reviewed-by: Shawn Nematbakhsh Reviewed-on: http://review.coreboot.org/4976 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/romstage/romstage.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc/intel/baytrail/romstage') diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 91637d51ae..8436c65d17 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -41,6 +41,7 @@ #include #include #include +#include static inline uint64_t timestamp_get(void) { @@ -94,6 +95,13 @@ static void program_base_addresses(void) pci_write_config32(lpc_dev, GBASE, reg); } +static void spi_init(void) +{ + const unsigned long bcr = SPI_BASE_ADDRESS + BCR; + /* Enable caching and prefetching in the SPI controller. */ + write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH); +} + static inline void mark_ts(struct romstage_params *rp, uint64_t ts) { struct romstage_timestamps *rt = &rp->ts; @@ -124,6 +132,8 @@ void * asmlinkage romstage_main(unsigned long bist, console_init(); + spi_init(); + set_max_freq(); punit_init(); -- cgit v1.2.3