From 4177db52a29b28a023a9ae84ed76c40ed6ce4daf Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 5 Feb 2014 14:55:26 -0600 Subject: baytrail/rambi: spi, charger, and audio updates baytrail: combine SPI configuration in romstage Reviewed-on: https://chromium-review.googlesource.com/185140 (cherry picked from commit 4e7f0e8ae1138e478ae7106d54719cf05e13b402) baytrail: lock down registers before handoff Reviewed-on: https://chromium-review.googlesource.com/185200 (cherry picked from commit 82cce4d2b46ccc554b71efa179b5d95756e2ad5e) baytrail: invoke SMM finalization on handoff Reviewed-on: https://chromium-review.googlesource.com/185201 (cherry picked from commit 1b50affb1fdda52a5986c9429713930ed517a86a) rambi: don't invoke SMM finalization Reviewed-on: https://chromium-review.googlesource.com/185202 (cherry picked from commit 6eff475dae7f4536eb846ccf6d51fce262b8ffef) rambi: remove handling of APM_CNT_FINALIZE Reviewed-on: https://chromium-review.googlesource.com/185203 (cherry picked from commit 9fc310d7e2730466cc7fcc84999502a2d4d08bab) baytrail: don't increment boot count on S3 resume Reviewed-on: https://chromium-review.googlesource.com/185381 (cherry picked from commit 940a0fa4df1ce335229eb6f80143b93a84ba358c) rambi: enable HDA device Reviewed-on: https://chromium-review.googlesource.com/184574 (cherry picked from commit 334f2a5c7c6540e744b6aaf7e1da0b55e1368196) baytrail: lock down spi controller according to mainboard Reviewed-on: https://chromium-review.googlesource.com/185631 (cherry picked from commit 696ece68cb6d522c248e800f168e675e4b4a7317) rambi: implement mainboard_get_spi_config() to lock dow spi controller Reviewed-on: https://chromium-review.googlesource.com/185632 (cherry picked from commit 1d9ba15858fd421a4fe5a47f7171273128e89524) baytrail: introduce ssus_disable_internal_pull() Reviewed-on: https://chromium-review.googlesource.com/185740 (cherry picked from commit 9d6056dd70b27183dab6a4656f4f9612ae870a4d) rambi: fix write-protect gpio reading at romstage Reviewed-on: https://chromium-review.googlesource.com/185741 (cherry picked from commit c64627689b1afec59be6fdab323d5492046f0bc7) baytrail: DPTF: implement charger current limit Reviewed-on: https://chromium-review.googlesource.com/185759 (cherry picked from commit 287e8936613a7a83281ff692b20383dacf7fcaf6) rambi: Enable charger participant and define states Reviewed-on: https://chromium-review.googlesource.com/185760 (cherry picked from commit 2f62a11927ecf10cb2c76a9f5d368d4050404137) baytrail: increase command wait timeout Reviewed-on: https://chromium-review.googlesource.com/185874 (cherry picked from commit 962a79ef72169b5d52fc746d1889d3b652fd9bcc) baytrail: make caching MRC data more robust Reviewed-on: https://chromium-review.googlesource.com/185875 (cherry picked from commit b5e10ad47b9e4f330caaee4faf69702f24d6bdd8) baytrail: upgrade MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/186391 (cherry picked from commit 8c1a62f1f4261d4f38aacbbb353c9d6218ec2885) rambi: instruct MRC to use weaker memory ODT settings Reviewed-on: https://chromium-review.googlesource.com/186420 (cherry picked from commit b9329126ca08d20ce1d8c5db0fcabd39140c7292) rambi: Move touch wakeup resource GPIO to separate device Reviewed-on: https://chromium-review.googlesource.com/186932 (cherry picked from commit ba44e2e04f9469c629cb61a911c8cd339f52b0ef) baytrail: Set some MSRs related to turbo power Reviewed-on: https://chromium-review.googlesource.com/186933 (cherry picked from commit 76b25df5a31914ae58d47d17af448216011e425c) baytrail: change power consumption number for ACPI_C3/C6FS. Reviewed-on: https://chromium-review.googlesource.com/186934 (cherry picked from commit 5192e2464fbb88ea6fc117070240c9733e34f065) baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device Reviewed-on: https://chromium-review.googlesource.com/186928 (cherry picked from commit 8d1ab5de1d43b0790d140f6d0e36a990a5049ece) baytrail: Disable P-state HW coordination on 4-core SKU Reviewed-on: https://chromium-review.googlesource.com/187575 (cherry picked from commit c19c0f1d7cb3cb2635766c186ba9598933424a78) baytrail: DPTF: Enable mainboard-specific _PDL Reviewed-on: https://chromium-review.googlesource.com/187576 (cherry picked from commit 5412ac5c07bee22017a0ee6d1e2433917b98ea87) rambi: Apply DPTF tuning parameters Reviewed-on: https://chromium-review.googlesource.com/187577 (cherry picked from commit 932a5a3803ceaf430ad2934b371ac0886c25efca) rambi : change lpe_codec_clk_freq to 19.2 Reviewed-on: https://chromium-review.googlesource.com/187594 (cherry picked from commit f64cb1ae77076ad5ec994670f4a83dc561ea80c4) Squashed 25 commits for baytrail/rambi. Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Duncan Laurie --- src/soc/intel/baytrail/romstage/romstage.c | 37 +++++++++++++++--------------- 1 file changed, 18 insertions(+), 19 deletions(-) (limited to 'src/soc/intel/baytrail/romstage') diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 3a1d65d8ab..1c08f339fd 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -98,9 +98,19 @@ static void program_base_addresses(void) static void spi_init(void) { + const unsigned long scs = SPI_BASE_ADDRESS + SCS; const unsigned long bcr = SPI_BASE_ADDRESS + BCR; - /* Enable caching and prefetching in the SPI controller. */ - write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH); + uint32_t reg; + + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); } static inline void mark_ts(struct romstage_params *rp, uint64_t ts) @@ -239,15 +249,17 @@ void romstage_common(struct romstage_params *params) mark_ts(params, timestamp_get()); -#if CONFIG_ELOG_BOOT_COUNT - boot_count_increment(); -#endif - ps = fill_power_state(); prev_sleep_state = chipset_prev_sleep_state(ps); printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); +#if CONFIG_ELOG_BOOT_COUNT + if (prev_sleep_state != 3) + boot_count_increment(); +#endif + + /* Initialize RAM */ raminit(params->mrc_params, prev_sleep_state); @@ -268,21 +280,8 @@ void romstage_common(struct romstage_params *params) timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3])); } -static void open_up_spi(void) -{ - const uintptr_t sbase = SPI_BASE_ADDRESS; - - /* Disable generating SMI when setting WPD bit. */ - write32(sbase + 0xf8, read32(sbase + 0xf8) & ~(1 << 7)); - /* Disable the SMM-only BIOS write and set WPD bit. */ - write32(sbase + 0xfc, 1 | (read32(sbase + 0xfc) & ~(1 << 5))); -} - void asmlinkage romstage_after_car(void) { - /* Allow BIOS to program SPI part. */ - open_up_spi(); - timestamp_add_now(TS_END_ROMSTAGE); /* Load the ramstage. */ -- cgit v1.2.3