From bd74a4b2d25268f7035a4478da31f27baac2aecc Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Fri, 6 Mar 2015 23:17:33 -0600
Subject: coreboot: common stage cache

Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.

Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
---
 src/soc/intel/baytrail/romstage/romstage.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/soc/intel/baytrail/romstage/romstage.c')

diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 029fee61ee..9c8bbc40ce 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -20,18 +20,18 @@
 #include <stddef.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
-#include <arch/cbfs.h>
 #include <arch/stages.h>
 #include <arch/early_variables.h>
 #include <console/console.h>
+#include <cbfs.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
 #if CONFIG_EC_GOOGLE_CHROMEEC
 #include <ec/google/chromeec/ec.h>
 #endif
 #include <elog.h>
-#include <ramstage_cache.h>
 #include <romstage_handoff.h>
+#include <stage_cache.h>
 #include <timestamp.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/gpio.h>
@@ -359,7 +359,7 @@ static void *setup_stack_and_mttrs(void)
 	return slot;
 }
 
-void ramstage_cache_invalid(struct ramstage_cache *cache)
+void ramstage_cache_invalid(void)
 {
 #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
 	/* Perform cold reset on invalid ramstage cache. */
-- 
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