From 7837be6cbb9dfacf66d0981e281c3d9a0a35767d Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 21 Oct 2013 22:32:00 -0500 Subject: baytrail: SMM support Initialize SMM on all CPUs by relocating the SMM region and setting SMRR on all the cores. Additionally SMI is enabled in the south cluster. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted rambi. Tested with DEBUG_SMI and noted power button turns off board while in firmware. Change-Id: I92e3460572feeb67d4a3d4d26af5f0ecaf7d3dd5 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/173983 Reviewed-on: http://review.coreboot.org/4892 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/soc/intel/baytrail/romstage/romstage.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/baytrail/romstage/romstage.c') diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 3ab726df91..0149f1f351 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -34,6 +34,7 @@ #include #include #include +#include static inline uint64_t timestamp_get(void) { @@ -277,13 +278,13 @@ struct ramstage_cache *ramstage_cache_location(long *size) { char *smm_base; /* 1MiB cache size */ - const long cache_size = (1 << 20); + const long cache_size = CONFIG_SMM_RESERVED_SIZE; /* Ramstage cache lives in TSEG region which is the definition of * cbmem_top(). */ smm_base = cbmem_top(); *size = cache_size; - return (void *)&smm_base[CONFIG_SMM_TSEG_SIZE - cache_size]; + return (void *)&smm_base[smm_region_size() - cache_size]; } void ramstage_cache_invalid(struct ramstage_cache *cache) -- cgit v1.2.3