From 26b49cc9a3f027ad6af56e5f6fd572805fe0f30f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 7 Jul 2020 17:17:51 +0200 Subject: soc/intel/baytrail: Align whitespace and comments This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/soc/intel/baytrail/include/soc/device_nvs.h | 2 +- src/soc/intel/baytrail/include/soc/iosf.h | 12 ++++++------ src/soc/intel/baytrail/include/soc/irq.h | 10 +++++++--- src/soc/intel/baytrail/include/soc/nvs.h | 2 +- src/soc/intel/baytrail/include/soc/pattrs.h | 10 ++++++---- src/soc/intel/baytrail/include/soc/pm.h | 24 ++++++++++++------------ 6 files changed, 33 insertions(+), 27 deletions(-) (limited to 'src/soc/intel/baytrail/include') diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h index b2f3bd2e48..6a5f1084a7 100644 --- a/src/soc/intel/baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/baytrail/include/soc/device_nvs.h @@ -35,7 +35,7 @@ typedef struct { u32 scc_bar0[3]; u32 lpe_bar0; - /* BAR 0 */ + /* BAR 1 */ u32 lpss_bar1[14]; u32 scc_bar1[3]; u32 lpe_bar1; diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 1d105a2487..15d77de03d 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -12,17 +12,17 @@ * MCR - control register * MDR - data register * MCRX - control register extension - * The extension regist is only used for addresses that don't fit into the - * 8 bit register address. + * The extension register is only used for addresses that don't fit + * into the 8 bit register address. */ #ifndef PCI_DEV #define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) #endif -#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC) +#define IOSF_PCI_DEV PCI_DEV(0, SOC_DEV, SOC_FUNC) #define MCR_REG 0xd0 #define IOSF_OPCODE(x) ((x) << 24) diff --git a/src/soc/intel/baytrail/include/soc/irq.h b/src/soc/intel/baytrail/include/soc/irq.h index ca4cac1442..967bc35341 100644 --- a/src/soc/intel/baytrail/include/soc/irq.h +++ b/src/soc/intel/baytrail/include/soc/irq.h @@ -11,6 +11,7 @@ #define PIRQF_APIC_IRQ 21 #define PIRQG_APIC_IRQ 22 #define PIRQH_APIC_IRQ 23 + /* The below IRQs are for when devices are in ACPI mode. Active low. */ #define LPE_DMA0_IRQ 24 #define LPE_DMA1_IRQ 25 @@ -110,9 +111,11 @@ # define SCIS_IRQ22 0x06 # define SCIS_IRQ23 0x07 -/* In each mainboard directory there should exist a header file irqroute.h that +/* + * In each mainboard directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which - * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ + * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. + */ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include @@ -135,9 +138,10 @@ extern const struct baytrail_irq_route global_baytrail_irq_route; .pic = { PIRQ_PIC_ROUTES, }, \ } +/* The following macros are used for ACPI by the ASL compiler */ #define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) #define PIRQ_PIC(pirq_, pic_irq_) \ [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index cdffc75768..41b827e5c9 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -48,7 +48,7 @@ struct __packed global_nvs { u8 unused[76]; - /* ChromeOS specific (0x100-0xfff)*/ + /* ChromeOS specific (0x100-0xfff) */ chromeos_acpi_t chromeos; /* Baytrail LPSS (0x1000) */ diff --git a/src/soc/intel/baytrail/include/soc/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h index c1ca7f45b7..d485484e0c 100644 --- a/src/soc/intel/baytrail/include/soc/pattrs.h +++ b/src/soc/intel/baytrail/include/soc/pattrs.h @@ -14,7 +14,8 @@ enum { IACORE_END }; -/* The pattrs structure is a common place to stash pertinent information +/* + * The pattrs structure is a common place to stash pertinent information * about the processor or platform. Instead of going to the source (msrs, cpuid) * every time an attribute is needed use the pattrs structure. */ @@ -32,8 +33,10 @@ struct pattrs { unsigned int bclk_khz; }; -/* This is just to hide the abstraction w/o relying on how the underlying - * storage is allocated. */ +/* + * This is just to hide the abstraction w/o relying on how the underlying + * storage is allocated. + */ #define PATTRS_GLOB_NAME __global_pattrs #define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME extern DEFINE_PATTRS; @@ -43,5 +46,4 @@ static inline const struct pattrs *pattrs_get(void) return &PATTRS_GLOB_NAME; } - #endif /* _PATTRS_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index 0481159416..5886fe52ab 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -204,21 +204,21 @@ #define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT #define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define USB_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ +#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */ +#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ #define SMI_STS 0x34 #define ALT_GPIO_SMI 0x38 #define UPRWC 0x3c -# define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable +# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ #define GPE_CTRL 0x40 #define PM2A_CNT_BLK 0x50 #define TCO_RLD 0x60 -- cgit v1.2.3