From 038e7247dc9705ff2d47dd90ec9a807f6feb52ba Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 29 Jul 2016 18:31:16 +0200 Subject: src/soc: Capitalize CPU, ACPI, RAM and ROM Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth --- src/soc/intel/baytrail/include/soc/iosf.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/baytrail/include') diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 3ad2110ded..436cc33477 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -185,11 +185,11 @@ void iosf_ssus_write(int reg, uint32_t val); #define BNOCACHE 0x23 /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ #define BUNIT_BMBOUND 0x25 -/* BMBOUND_HI describes the available ram above 4GiB. It has a +/* BMBOUND_HI describes the available RAM above 4GiB. It has a * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB * granularity care needs to be taken with the e820 map to account for a hole - * in the ram. */ + * in the RAM. */ #define BUNIT_BMBOUND_HI 0x26 #define BUNIT_MMCONF_REG 0x27 /* The SMMRR registers define the SMM region in MiB granularity. */ -- cgit v1.2.3