From fda56a6bfdee8a1b0afea3618e466f2813368aeb Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 24 Sep 2013 12:29:57 -0500 Subject: baytrail: add common pci_operations The coreboot device modeling for pci devices wants a pci_operations structure for all devices. This structure just sets the subsystem vendor and device id. Add a common one that all the other pci drivers can use for Bay Trail. BUG=chrome-os-partner:22860 BRANCH=None TEST=Built and booted while utilizing this new structure. Change-Id: I39949cbdb83b3acb93fe4034eb4278d45369e321 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/170428 Reviewed-on: http://review.coreboot.org/4851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/baytrail/chip.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/baytrail/chip.c') diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 5a5c364f5f..09c36dfd5d 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -52,7 +52,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, .init = cpu_bus_init, - .scan_bus = 0, + .scan_bus = NULL, }; @@ -72,3 +72,18 @@ struct chip_operations soc_intel_baytrail_ops = { CHIP_NAME("Intel BayTrail SoC") .enable_dev = enable_dev, }; + +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +struct pci_operations soc_pci_ops = { + .set_subsystem = &pci_set_subsystem, +}; -- cgit v1.2.3