From c0270aa6d0e183ceb04566b6e9e3939bd9215d35 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 4 Oct 2013 11:15:48 -0500 Subject: baytrail: load microcode in bootblock Start loading microcode in the bootblock. This way no caching has been set up and cache-as-ram mode will be running in a validated configruation (with ucode patch). BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and booted. Confirmed microcode is loaded. Change-Id: I6fd1d8e55bcc9d799b11d9faed771ac50dc120a2 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/171861 Reviewed-by: Shawn Nematbakhsh Reviewed-on: http://review.coreboot.org/4863 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/baytrail/bootblock/bootblock.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/baytrail/bootblock/bootblock.c') diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 70ccc21f8b..fa0d9eee8d 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -22,6 +22,7 @@ #include #include #include +#include static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) { @@ -49,12 +50,10 @@ static void enable_rom_caching(void) wrmsr(MTRRdefType_MSR, msr); } -static void bootblock_cpu_init(void) +static void setup_mmconfig(void) { uint32_t reg; - enable_rom_caching(); - /* Set up the MMCONF range. The register lives in the BUNIT. The * IO variant of the config access needs to be used initially to * properly configure as the IOSF access registers live in PCI @@ -68,3 +67,13 @@ static void bootblock_cpu_init(void) IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } + +static void bootblock_cpu_init(void) +{ + /* Allow memory-mapped PCI config access. */ + setup_mmconfig(); + + /* Load microcode before any caching. */ + intel_update_microcode_from_cbfs(); + enable_rom_caching(); +} -- cgit v1.2.3