From ba170b477514239daf92dc7f4333318c96f275bc Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 23 Sep 2013 14:15:42 -0500 Subject: baytrail: cache ROM space early in bootblock Take advantage of the cache early in bootblock. The intent is to speed up cbfs walking when trying to locate romstage. BUG=chrome-os-partner:22857 BRANCH=None TEST=Built and booted. Change-Id: If03210103c9782390230915db3b4a9759d172dce Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/170426 Reviewed-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/4849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/baytrail/bootblock/bootblock.c | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'src/soc/intel/baytrail/bootblock/bootblock.c') diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 66120d9125..70ccc21f8b 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -18,12 +18,43 @@ */ #include +#include +#include +#include #include +static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +{ + msr_t basem, maskm; + basem.lo = base | type; + basem.hi = 0; + wrmsr(MTRRphysBase_MSR(reg), basem); + maskm.lo = ~(size - 1) | MTRRphysMaskValid; + maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(reg), maskm); +} + +static void enable_rom_caching(void) +{ + msr_t msr; + + disable_cache(); + /* Why only top 4MiB ? */ + set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); + enable_cache(); + + /* Enable Variable MTRRs */ + msr.hi = 0x00000000; + msr.lo = 0x00000800; + wrmsr(MTRRdefType_MSR, msr); +} + static void bootblock_cpu_init(void) { uint32_t reg; + enable_rom_caching(); + /* Set up the MMCONF range. The register lives in the BUNIT. The * IO variant of the config access needs to be used initially to * properly configure as the IOSF access registers live in PCI -- cgit v1.2.3