From 26b49cc9a3f027ad6af56e5f6fd572805fe0f30f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 7 Jul 2020 17:17:51 +0200 Subject: soc/intel/baytrail: Align whitespace and comments This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/soc/intel/baytrail/bootblock/bootblock.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'src/soc/intel/baytrail/bootblock/bootblock.c') diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 54e7261d3b..0f3980cefb 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -13,10 +13,11 @@ static void setup_mmconfig(void) { uint32_t reg; - /* Set up the MMCONF range. The register lives in the BUNIT. The - * IO variant of the config access needs to be used initially to - * properly configure as the IOSF access registers live in PCI - * config space. */ + /* + * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the + * config access needs to be used initially to properly configure as the IOSF access + * registers live in PCI config space. + */ reg = 0; /* Clear the extended register. */ pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); @@ -98,11 +99,11 @@ static void byt_config_com1_and_enable(void) just pick the one that is called first. */ void bootblock_early_northbridge_init(void) { - /* Allow memory-mapped PCI config access. */ + /* Allow memory-mapped PCI config access */ setup_mmconfig(); + /* Early chipset initialization */ program_base_addresses(); - tco_disable(); if (CONFIG(ENABLE_BUILTIN_COM1)) -- cgit v1.2.3