From dc866cff31e26de7cf95bbd0675037d8066f7dc8 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 12 Nov 2013 20:21:53 -0600 Subject: baytrail: first pass at lpss device initialization This commit does the common parts for all LPSS devices that are enabled: enable snoop in IOSF and enable power management. Additionally, the i2c devices are taken out of reset. BUG=chrome-os-partner:23790 BRANCH=None TEST=Built and booted with modified kernel-next. I2C bus devices show up and I see 0x10 on one of the buses. Change-Id: I540caea6a8666f5684dc5cee683a6b085dfac6de Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/176424 Reviewed-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/4969 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/baytrail/Makefile.inc') diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index a6560ff26d..1f643f9ae4 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += acpi.c ramstage-y += lpe.c ramstage-y += scc.c ramstage-y += emmc.c +ramstage-y += lpss.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c -- cgit v1.2.3