From cffe795dc1516607421bf770eab45076087fc461 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 11 Dec 2013 17:15:45 -0800 Subject: baytrail: initialize perf/power registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the reference code all these registers need to be set to their best known values. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Suspend and wake. No idea about observable impact yet. Change-Id: I0e31505a165eee1d177e5d726edcfa6947430476 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/179749 Reviewed-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/5008 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/baytrail/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/baytrail/Makefile.inc') diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 48fb4b448a..e2a949f74b 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += emmc.c ramstage-y += lpss.c ramstage-y += pcie.c ramstage-y += sd.c +ramstage-y += perf_power.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c -- cgit v1.2.3