From 9fd7c0f18ee8665f2e4dc311ae906412f2b0a0a1 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 16 Jan 2014 09:47:39 -0800 Subject: baytrail: Add SOC thermal settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apply the SOC thermal settings from DPTF reference code for SdpProfile=4 and adjust graphics PUNIT setting to match. BUG=chrome-os-partner:17279 BRANCH=baytrail TEST=boot on rambi and check for valid GPU power values from DPTF Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8 Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/182786 Reviewed-by: Aaron Durbin Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/5052 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Kyösti Mälkki --- src/soc/intel/baytrail/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/baytrail/Makefile.inc') diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 974d33dfde..f93435be80 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += emmc.c ramstage-y += lpss.c ramstage-y += pcie.c ramstage-y += sd.c +ramstage-y += dptf.c ramstage-y += perf_power.c ramstage-y += stage_cache.c romstage-y += stage_cache.c -- cgit v1.2.3