From 6ecdb68562989aec1362e3a99f3ed2e0012e1191 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 10 Oct 2013 20:54:57 -0500 Subject: baytrail: add reset support Bay Trail has the following types of resets it supports: - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but with ETR[20] set. While these are documented this support currently provides support for 2nd soft reset as well as cold and warm reset. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted. Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/172710 Reviewed-by: Shawn Nematbakhsh Reviewed-on: http://review.coreboot.org/4878 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/baytrail/Kconfig') diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 4cd21334fc..293ed211b5 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_MICROCODE_IN_CBFS select DYNAMIC_CBMEM select HAVE_SMI_HANDLER + select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES -- cgit v1.2.3