From 4f14cd8a39e65811af08296633842289efa42927 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 18 Dec 2019 19:40:48 +0200 Subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/baytrail/Kconfig | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'src/soc/intel/baytrail/Kconfig') diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 94ed887d5c..4e9223750e 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -124,17 +124,6 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The baytrail romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n -- cgit v1.2.3