From ffb3a2d22506a86e205a757029f60abccfef0486 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@chromium.org>
Date: Mon, 24 Oct 2016 15:28:23 -0700
Subject: soc/intel/apollolake: Enable write-protect SPI flash range support

Use intel common infrastructure to enable support for write-protecting
SPI flash range. Also, enable this protection for RW_MRC_CACHE.

BUG=chrome-os-partner:58896
TEST=Verified that write to RW_MRC_CACHE fails in OS using
"flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin"

Change-Id: I35df12bc295d141e314ec2cb092d904842432394
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17117
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
---
 src/soc/intel/apollolake/Kconfig           |  2 ++
 src/soc/intel/apollolake/include/soc/spi.h |  3 +++
 src/soc/intel/apollolake/spi.c             | 14 ++++++++++++++
 3 files changed, 19 insertions(+)

(limited to 'src/soc/intel/apollolake')

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 6c178c31d4..187214ae4e 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -34,6 +34,7 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_SMI_HANDLER
 	select MMCONF_SUPPORT
 	select MMCONF_SUPPORT_DEFAULT
+	select MRC_SETTINGS_PROTECT
 	select NO_FIXED_XIP_ROM_SIZE
 	select NO_XIP_EARLY_STAGES
 	select PARALLEL_MP
@@ -52,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_LPSS_I2C
 	select SOC_INTEL_COMMON_SMI
+	select SOC_INTEL_COMMON_SPI_PROTECT
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
 	select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h
index cc508e1b67..4f16a85717 100644
--- a/src/soc/intel/apollolake/include/soc/spi.h
+++ b/src/soc/intel/apollolake/include/soc/spi.h
@@ -33,9 +33,12 @@
 #define SPIBAR_HSFSTS_CTL		0x04
 #define SPIBAR_FADDR			0x08
 #define SPIBAR_FDATA(n)			(0x10 + ((n) & 0xf) * 4)
+#define SPIBAR_FPR_BASE			0x84
 #define SPIBAR_PTINX			0xcc
 #define SPIBAR_PTDATA			0xd0
 
+#define SPIBAR_FPR_MAX			5
+
 /* Bit definitions and masks for BIOS_BFPREG register. */
 #define  SPIBAR_BFPREG_PRB_MASK	(0x7fff)
 #define  SPIBAR_BFPREG_PRL_SHIFT	(16)
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
index 139d36cd37..85bc0b6a32 100644
--- a/src/soc/intel/apollolake/spi.c
+++ b/src/soc/intel/apollolake/spi.c
@@ -21,6 +21,7 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <soc/intel/common/spi.h>
 #include <soc/pci_devs.h>
 #include <soc/spi.h>
 #include <spi_flash.h>
@@ -393,3 +394,16 @@ int spi_read_status(uint8_t *status)
 
 	return 0;
 }
+
+int spi_get_fpr_info(struct fpr_info *info)
+{
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	if (!ctx->mmio_base)
+		return -1;
+
+	info->base = ctx->mmio_base + SPIBAR_FPR_BASE;
+	info->max = SPIBAR_FPR_MAX;
+
+	return 0;
+}
-- 
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