From f699c14c03a78549b0e5ed32cf9714473127c618 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 8 Jun 2018 17:57:37 +0530 Subject: soc/intel/common/block/cpu: Add option to skip coreboot AP init SoC users from IOTG team is looking forward for a solution to skip coreboot AP initialization flow and make use of FSPS-UPD to perform AP reset. TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs out of reset. Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/26644 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/chip.c | 5 +++-- src/soc/intel/apollolake/chip.h | 7 ------- 2 files changed, 3 insertions(+), 9 deletions(-) (limited to 'src/soc/intel/apollolake') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 31b6b1747f..081bba373e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -28,9 +28,10 @@ #include #include #include +#include #include -#include #include +#include #include #include #include @@ -614,7 +615,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) silconfig->MonitorMwaitEnable = 0; - silconfig->SkipMpInit = !cfg->use_fsp_mp_init; + silconfig->SkipMpInit = !chip_get_fsp_mp_init(); /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 4f586acfd1..61ddedaf49 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -150,13 +150,6 @@ struct soc_intel_apollolake_config { * (1) Power * (2) Power & Performance */ enum pnp_settings pnp_settings; - - /* - * Option for mainboard to skip coreboot MP initialization - * 0 = Make use of coreboot MP Init - * 1 = Make use of FSP MP Init - */ - uint8_t use_fsp_mp_init; }; typedef struct soc_intel_apollolake_config config_t; -- cgit v1.2.3