From ec2947fb075838d1ea78754113aef6cf000cf522 Mon Sep 17 00:00:00 2001 From: Abhay Kumar Date: Thu, 14 Jul 2016 18:43:54 -0700 Subject: soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume Do not pass VBT table to fsp in normal mode and S3 resume so that PEIM GFX will not get initialized. Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e Signed-off-by: Abhay Kumar Reviewed-on: https://review.coreboot.org/14575 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/apollolake/chip.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/soc/intel/apollolake') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 544cd133c8..10b71fbc8d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -194,8 +194,7 @@ static void soc_init(void *data) struct global_nvs_t *gnvs; /* Save VBT info and mapping */ - if (locate_vbt(&vbt_rdev) != CB_ERR) - vbt = rdev_mmap_full(&vbt_rdev); + vbt = vbt_get(&vbt_rdev); /* Snapshot the current GPIO IRQ polarities. FSP is setting a * default policy that doesn't honor boards' requirements. */ -- cgit v1.2.3