From c4276a3fdc803213d706491c3f83534ce2870f24 Mon Sep 17 00:00:00 2001 From: Shamile Khan Date: Wed, 14 Mar 2018 18:09:19 -0700 Subject: soc/intel/apollolake: Add PCIe de-emphasis enable configuration. PCIe de-emphasis is enabled by default. Thunderpeak Wi-Fi requires it to be disabled. Therefore allow it to be configured via a device tree setting. TEST=On GLKRVP, verify Thunderpeak Wi-Fi card shows up in lspci when de-emphasis is disabled in device tree. Change-Id: Iae204768dfe00a638c764644c44c7cda269e73e0 Signed-off-by: Shamile Khan Reviewed-on: https://review.coreboot.org/25185 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/chip.c | 11 +++++++++++ src/soc/intel/apollolake/chip.h | 3 +++ 2 files changed, 14 insertions(+) (limited to 'src/soc/intel/apollolake') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index af145c0259..cac2f1134b 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -502,6 +502,17 @@ static void glk_fsp_silicon_init_params_cb( struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { silconfig->Gmm = 0; + + /* On Geminilake, we need to override the default FSP PCIe de-emphasis + * settings using the device tree settings. This is because PCIe + * de-emphasis is enabled by default and Thunderpeak PCIe WiFi detection + * requires de-emphasis disabled. If we make this change common to both + * Apollolake and Geminilake, then we need to add mainboard device tree + * de-emphasis settings of 1 to Apollolake systems. + */ + memcpy(silconfig->PcieRpSelectableDeemphasis, + cfg->pcie_rp_deemphasis_enable, + sizeof(silconfig->PcieRpSelectableDeemphasis)); } void __attribute__((weak)) mainboard_devtree_update(struct device *dev) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index fe845ab06c..f354538aa4 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -49,6 +49,9 @@ struct soc_intel_apollolake_config { /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable). */ uint8_t pcie_rp_hotplug_enable[MAX_PCIE_PORTS]; + /* De-emphasis enable configuration for each PCIe root port */ + uint8_t pcie_rp_deemphasis_enable[MAX_PCIE_PORTS]; + /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. * [6:0] SDR mode Number of dealy elements.Each = 125pSec. */ -- cgit v1.2.3