From 97012bd019896c589a4b736f17f5c1ad8f378924 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 4 Nov 2019 22:07:29 +0100 Subject: soc/intel/apollolake: make use of common cbmem_top_chipset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This replaces apollolake's own implementation of cbmem_top_chipset and selects the common code one. Change-Id: I11d12a6c8414a98d38be8b0dbf6dc57cd2efc5d6 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36618 Reviewed-by: Werner Zeh Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/Makefile.inc | 4 ---- src/soc/intel/apollolake/memmap.c | 35 ----------------------------------- 3 files changed, 1 insertion(+), 39 deletions(-) delete mode 100644 src/soc/intel/apollolake/memmap.c (limited to 'src/soc/intel/apollolake') diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 026f6da669..cd0c9cd0e8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -84,6 +84,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_TCO diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index ef81e32abd..24375b3599 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += gspi.c romstage-y += heci.c romstage-y += i2c.c romstage-y += uart.c -romstage-y += memmap.c romstage-y += meminit.c ifeq ($(CONFIG_SOC_INTEL_GLK),y) romstage-y += meminit_util_glk.c @@ -59,7 +58,6 @@ ramstage-y += gspi.c ramstage-y += heci.c ramstage-y += i2c.c ramstage-y += lpc.c -ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c ramstage-y += nhlt.c @@ -73,7 +71,6 @@ ramstage-y += xdci.c ramstage-y += sd.c ramstage-y += xhci.c -postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-y += i2c.c @@ -86,7 +83,6 @@ verstage-y += car.c verstage-y += i2c.c verstage-y += gspi.c verstage-y += heci.c -verstage-y += memmap.c verstage-y += mmap_boot.c verstage-y += uart.c verstage-y += pmutil.c diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c deleted file mode 100644 index de6a7d1f19..0000000000 --- a/src/soc/intel/apollolake/memmap.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "chip.h" - -void *cbmem_top_chipset(void) -{ - void *tolum = (void *)sa_get_tseg_base(); - - if (!CONFIG(SOC_INTEL_GLK)) - return tolum; - - /* FSP allocates 2x PRMRR Size Memory for alignment */ - tolum -= get_prmrr_size() * 2; - - return tolum; -} -- cgit v1.2.3