From 7736bfc443a913a9cde46406bcfc38015ec71f47 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Tue, 22 Oct 2019 23:05:06 +0200 Subject: soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/chip.h | 12 ------------ src/soc/intel/apollolake/cpu.c | 11 +++-------- src/soc/intel/apollolake/memmap.c | 7 ++----- src/soc/intel/apollolake/romstage.c | 4 +--- 5 files changed, 7 insertions(+), 28 deletions(-) (limited to 'src/soc/intel/apollolake') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 5530e5c5ab..7655d5aa9a 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) +subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 85cfff9af5..e5045d01b1 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -139,18 +139,6 @@ struct soc_intel_apollolake_config { /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; - /* PRMRR size setting with three options - * 0x02000000 - 32MiB - * 0x04000000 - 64MiB - * 0x08000000 - 128MiB */ - uint32_t PrmrrSize; - - /* Enable SGX feature. - * Enabling SGX feature is 2 step process, - * (1) set sgx_enable = 1 - * (2) set PrmrrSize to supported size */ - uint8_t sgx_enable; - /* Select PNP Settings. * (0) Performance, * (1) Power diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 6e826b863c..0b9466c4c5 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -72,13 +72,10 @@ static const struct reg_script core_msr_script[] = { void soc_core_init(struct device *cpu) { - config_t *conf = config_of_soc(); - /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ - if ((CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) || - acpi_get_sleep_type() == ACPI_S5) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) || acpi_get_sleep_type() == ACPI_S5) mca_configure(); /* Set core MSRs */ @@ -91,7 +88,7 @@ void soc_core_init(struct device *cpu) enable_pm_timer_emulation(); /* Configure Core PRMRR for SGX. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) prmrr_core_configure(); /* Set Max Non-Turbo ratio if RAPL is disabled. */ @@ -255,11 +252,9 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, static void post_mp_init(void) { - config_t *conf = config_of_soc(); - smm_southbridge_enable(PWRBTN_EN | GBL_EN); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) mp_run_on_all_cpus(sgx_configure, NULL); } diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 567ff1ebc6..de6a7d1f19 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -16,23 +16,20 @@ */ #include +#include #include #include "chip.h" void *cbmem_top_chipset(void) { - const config_t *config; void *tolum = (void *)sa_get_tseg_base(); if (!CONFIG(SOC_INTEL_GLK)) return tolum; - config = config_of_soc(); - /* FSP allocates 2x PRMRR Size Memory for alignment */ - if (config->sgx_enable) - tolum -= config->PrmrrSize * 2; + tolum -= get_prmrr_size() * 2; return tolum; } diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 8418919bd2..258f4ffaf3 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -269,9 +269,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - const config_t *config = config_of_soc(); - - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); /* * CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. -- cgit v1.2.3