From 63032439f4278125b3a01d33d056761dd1ae8cba Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Sun, 11 Oct 2020 17:34:54 +0200 Subject: {cpu,soc}/intel: replace AES-NI locking by common implemenation call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deduplicate code by using the new common cpu code implementation of AES-NI locking. Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/apollolake/cpu.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'src/soc/intel/apollolake') diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 72f983f3dd..0ae170b44d 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -43,12 +44,6 @@ static const struct reg_script core_msr_script[] = { #endif /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), - /* - * Enable and Lock the Advanced Encryption Standard (AES-NI) - * feature register - */ - REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK, - FEATURE_CONFIG_LOCK), REG_SCRIPT_END }; @@ -62,6 +57,9 @@ void soc_core_init(struct device *cpu) /* Set core MSRs */ reg_script_run(core_msr_script); + + set_aesni_lock(); + /* * Enable ACPI PM timer emulation, which also lets microcode know * location of ACPI_BASE_ADDRESS. This also enables other features -- cgit v1.2.3