From 3eff037f8cbe99f72626c0f25c0989ea638599ef Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 10 Sep 2019 15:51:17 +0530 Subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch removes dedicated function call to make TSEG region cache from soc and refers to postcar_enable_tseg_cache(). BUG=b:140008206 Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/35025 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Kyösti Mälkki --- src/soc/intel/apollolake/memmap.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) (limited to 'src/soc/intel/apollolake') diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index bda43bbdbf..905fa64571 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -53,8 +53,6 @@ void smm_region(uintptr_t *start, size_t *size) void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; /* * We need to make sure ramstage will be run cached. At this point exact @@ -67,13 +65,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } -- cgit v1.2.3