From 310c7637daba6ba4e9249928e5cd0e45ef4661e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 1 Oct 2020 22:28:03 +0200 Subject: soc/intel: deduplicate ACPI timer emulation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/pm.h | 2 -- src/soc/intel/apollolake/pmutil.c | 18 ------------------ 3 files changed, 1 insertion(+), 20 deletions(-) (limited to 'src/soc/intel/apollolake') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 79fab1a9d1..64889e56f9 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -10,6 +10,7 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c +bootblock-y += ../common/block/cpu/pm_timer_emulation.c bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += car.c bootblock-y += heci.c diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index aaf62583e6..748f76adba 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -234,8 +234,6 @@ struct chipset_power_state { void pch_log_state(void); -void enable_pm_timer_emulation(void); - /* STM Support */ uint16_t get_pmbase(void); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index e0de93eae4..6e96b57a07 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -178,24 +178,6 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, return prev_sleep_state; } -void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - static int rtc_failed(uint32_t gen_pmcon1) { return !!(gen_pmcon1 & RPS); -- cgit v1.2.3