From 117a66070add9e16b8dbec6425fa34ea25c0fa5a Mon Sep 17 00:00:00 2001 From: Franklin He Date: Mon, 16 Mar 2020 12:31:01 +1100 Subject: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake Enables Gaussian Mixture Model (GMM) if the pci device is enabled in the devicetree for Gemini Lake This ports commit 03ddd190fd6a2e91b16e6fd8a101cf4e11d7cd7b BUG=b:151115705 BRANCH=none TEST=Flashed to Chromebook, PCI device enabled in cbmem, userspace app that uses device still works Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392 Signed-off-by: Franklin He Reviewed-on: https://review.coreboot.org/c/coreboot/+/39579 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/chip.c | 4 +++- src/soc/intel/apollolake/include/soc/pci_devs.h | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/apollolake') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 178ccac066..5a652608eb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -612,6 +612,7 @@ static void glk_fsp_silicon_init_params_cb( { #if CONFIG(SOC_INTEL_GLK) uint8_t port; + struct device *dev; for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { if (!cfg->usb2eye[port].Usb20OverrideEn) @@ -627,7 +628,8 @@ static void glk_fsp_silicon_init_params_cb( cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; } - silconfig->Gmm = 0; + dev = pcidev_path_on_root(SA_GLK_DEVFN_GMM); + silconfig->Gmm = dev ? dev->enabled : 0; /* On Geminilake, we need to override the default FSP PCIe de-emphasis * settings using the device tree settings. This is because PCIe diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 6544b7a019..12a4e8db83 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -46,6 +46,10 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_GLK_DEV_SLOT_GMM 0x03 +#define SA_GLK_DEVFN_GMM PCI_DEVFN(SA_GLK_DEV_SLOT_GMM, 0) +#define SA_GLK_DEV_GMM PCI_DEV(0, SA_GLK_DEV_SLOT_GMM, 0) + /* PCH Devices */ #define PCH_DEV_SLOT_NPK 0x00 -- cgit v1.2.3