From 752dc8e4258b708dc4a96b3d929163b1560492ae Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Wed, 12 Jul 2017 14:27:09 +0530 Subject: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros Rename BAR0 and BAR2 SRAM base and size macros to align with the spec. * PMC_SRAM_BASE_0 -> SRAM_BASE_0 * PMC_SRAM_SIZE_0 -> SRAM_SIZE_0 * PMC_SRAM_BASE_1 -> SRAM_BASE_2 * PMC_SRAM_SIZE_1 -> SRAM_SIZE_2 Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/20539 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/sram.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/soc/intel/apollolake/sram.c') diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c index 0225327550..70e1330549 100644 --- a/src/soc/intel/apollolake/sram.c +++ b/src/soc/intel/apollolake/sram.c @@ -26,13 +26,13 @@ static void read_resources(device_t dev) pci_dev_read_resources(dev); res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = PMC_SRAM_BASE_0; - res->size = PMC_SRAM_SIZE_0; + res->base = SRAM_BASE_0; + res->size = SRAM_SIZE_0; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, PCI_BASE_ADDRESS_2); - res->base = PMC_SRAM_BASE_1; - res->size = PMC_SRAM_SIZE_1; + res->base = SRAM_BASE_2; + res->size = SRAM_SIZE_2; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } @@ -51,7 +51,7 @@ static void set_resources(device_t dev) pci_write_config32(dev, res->index, res->base); dev->command |= PCI_COMMAND_MEMORY; res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, " SRAM BAR 1"); + report_resource_stored(dev, res, " SRAM BAR 2"); } static const struct device_operations device_ops = { -- cgit v1.2.3