From efa606b77b93254d0e378ceab851753886f5efec Mon Sep 17 00:00:00 2001 From: Ravi Sarawadi Date: Fri, 4 Aug 2017 16:26:09 -0700 Subject: soc/intel/common/block: Add LPC Common code and use it for APL Add LPC common code to be shared across Intel platforms. Also add LPC library functions to be shared across platforms. Use common LPC code for Apollo Lake soc. Update existing Apollolake mainboard variants {google,intel,siemens} to use new common LPC header file. Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a Signed-off-by: Ravi Sarawadi Reviewed-on: https://review.coreboot.org/20659 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/romstage.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) (limited to 'src/soc/intel/apollolake/romstage.c') diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 59278a6942..2017d84d18 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -38,7 +39,6 @@ #include #include #include -#include #include #include #include @@ -96,17 +96,8 @@ static void soc_early_romstage_init(void) pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | P2SB_HPTC_ADDRESS_ENABLE); - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) { - /* - * I/O Decode Range Register for LPC - * ComA Range 3F8h-3FFh [2:0] - * ComB Range 2F8h-2FFh [6:4] - */ - pci_write_config16(PCH_DEV_LPC, REG_IO_DECODE, - IOD_COMA_RANGE | IOD_COMB_RANGE); - /* Enable ComA and ComB Port */ - lpc_enable_fixed_io_ranges(IOE_COMA_EN | IOE_COMB_EN); - } + if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); } static void disable_watchdog(void) -- cgit v1.2.3