From 0f593c22a8a88068ffdf73f87ee9ce98c343a977 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 17 Jun 2016 15:30:13 -0700 Subject: soc/intel/apollolake: Add utility functions for global reset Apollolake defines Global Reset where Host, TXE and PMC are reset. During boot we may need to trigger a global reset as part of platform initialization (or for error handling). Add functions to trigger global reset, enable/disable it and lock global reset bit. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I84296cd1560a0740f33ef6b488f15f99d397998d Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/15198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/pmutil.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'src/soc/intel/apollolake/pmutil.c') diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 6e47911fcd..84ac4b77a1 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -365,3 +365,34 @@ int vboot_platform_is_resuming(void) typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; return typ == SLP_TYP_S3; } + +/* + * If possible, lock 0xcf9. Once the register is locked, it can't be changed. + * This lock is reset on cold boot, hard reset, soft reset and Sx. + */ +void global_reset_lock(void) +{ + uintptr_t etr = read_pmc_mmio_bar() + ETR; + uint32_t reg; + + reg = read32((void *)etr); + if (reg & CF9_LOCK) + return; + reg |= CF9_LOCK; + write32((void *)etr, reg); +} + +/* + * Enable or disable global reset. If global reset is enabled, hard reset and + * soft reset will trigger global reset, where both host and TXE are reset. + * This is cleared on cold boot, hard reset, soft reset and Sx. + */ +void global_reset_enable(bool enable) +{ + uintptr_t etr = read_pmc_mmio_bar() + ETR; + uint32_t reg; + + reg = read32((void *)etr); + reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; + write32((void *)etr, reg); +} -- cgit v1.2.3