From 7736bfc443a913a9cde46406bcfc38015ec71f47 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Tue, 22 Oct 2019 23:05:06 +0200 Subject: soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/apollolake/memmap.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'src/soc/intel/apollolake/memmap.c') diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 567ff1ebc6..de6a7d1f19 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -16,23 +16,20 @@ */ #include +#include #include #include "chip.h" void *cbmem_top_chipset(void) { - const config_t *config; void *tolum = (void *)sa_get_tseg_base(); if (!CONFIG(SOC_INTEL_GLK)) return tolum; - config = config_of_soc(); - /* FSP allocates 2x PRMRR Size Memory for alignment */ - if (config->sgx_enable) - tolum -= config->PrmrrSize * 2; + tolum -= get_prmrr_size() * 2; return tolum; } -- cgit v1.2.3