From ffb3a2d22506a86e205a757029f60abccfef0486 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 24 Oct 2016 15:28:23 -0700 Subject: soc/intel/apollolake: Enable write-protect SPI flash range support Use intel common infrastructure to enable support for write-protecting SPI flash range. Also, enable this protection for RW_MRC_CACHE. BUG=chrome-os-partner:58896 TEST=Verified that write to RW_MRC_CACHE fails in OS using "flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin" Change-Id: I35df12bc295d141e314ec2cb092d904842432394 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/17117 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/include/soc/spi.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h index cc508e1b67..4f16a85717 100644 --- a/src/soc/intel/apollolake/include/soc/spi.h +++ b/src/soc/intel/apollolake/include/soc/spi.h @@ -33,9 +33,12 @@ #define SPIBAR_HSFSTS_CTL 0x04 #define SPIBAR_FADDR 0x08 #define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) +#define SPIBAR_FPR_BASE 0x84 #define SPIBAR_PTINX 0xcc #define SPIBAR_PTDATA 0xd0 +#define SPIBAR_FPR_MAX 5 + /* Bit definitions and masks for BIOS_BFPREG register. */ #define SPIBAR_BFPREG_PRB_MASK (0x7fff) #define SPIBAR_BFPREG_PRL_SHIFT (16) -- cgit v1.2.3