From e27c096b7f20e5f5424f1e912d7a88d820285e71 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Thu, 23 Aug 2018 15:33:53 +0200 Subject: siemens/mc_apl1: Correct the Tx signal from SATA interface Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/28285 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Alex Thiessen --- src/soc/intel/apollolake/include/soc/pcr_ids.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index f6c990e495..dba69b1ecc 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -33,6 +33,7 @@ #define PID_ITSS 0xD0 #define PID_RTC 0xD1 #define PID_LPC 0xD2 +#define PID_MODPHY 0xA5 #define PID_AUNIT 0x4d #define PID_BUNIT 0x4c -- cgit v1.2.3