From b72c67b713c7a651416be28831d80a77ef1ce617 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 12 Jul 2016 17:32:52 -0500 Subject: soc/intel/apollolake: set gpio interrupt polarity in ITSS For APIC routed gpios, set the corresponding interrupt polarity for the associated IRQ based on the gpio pad's invert setting. This allows for the APIC redirection entries to match the hardware active polarity once the double inversion takes place to meet apollolake interrupt triggering constraints. BUG=chrome-os-partner:54955 Change-Id: I69c395b6f861946d4774a4206cf8f5f721c6f5f4 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15648 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/include/soc/gpio_defs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index c6e2c3cf91..48e08e783e 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -75,6 +75,7 @@ #define PAD_CFG0_RESET_PLTRST (2 << 30) #define PAD_CFG0_RESET_RSMRST (3 << 30) +#define PAD_CFG1_IRQ_MASK (0xff << 0) #define PAD_CFG1_PULL_MASK (0xf << 10) #define PAD_CFG1_PULL_NONE (0x0 << 10) #define PAD_CFG1_PULL_DN_5K (0x2 << 10) -- cgit v1.2.3